1. Field of the Invention
This invention relates in general to the field of information storage, and more particularly to baseline wander correction and reduction of dc noise components in Hard Disk Drive (HDD) read channels.
2. Description of the Related Art
Hard disk drives (HDD) typically comprise at least one disk having a magnetic medium for storing information, a spindle, a controller for controlling disk rotational speed, a transducing head (for reading and writing data), a servo actuator assembly including a positioning controller for positioning the head over the appropriate disk track, and data channels for transmitting data to and from the disk. The transducing head reads data from and writes data to the disk in data blocks having either fixed or variable length. A data block comprises a preamble (for acquiring timing signals), timing bits, a position error field, address bits, data bits, and error correction bits. Data blocks are recorded in sectors in concentric tracks. A track may comprise several sectors. The number of sectors may depend on the radial location of the track on the disk. FIG. 1 shows a typical HDD as described above.
Data channels on HDD transmit and receive data via a communication medium. HDD and communication systems utilize similar techniques to encode data for storage and retrieval or for transmission and reception wherein data is encoded into a form in which it may be easily manipulated. Most modern applications of such systems encode data as numeric or digital information, wherein discrete numeric values are used to represent user data.
The storage or communication media do not directly manipulate such digital data. Rather, these media store or transmit analog signals representative of the digital data. For example, encoded digital information may be represented as magnetic flux transitions stored on a magnetic disk of an HDD. Two known ways of recording data magnetically on a disk are longitudinal recording and perpendicular recording. In longitudinal recording, as the name implies flux transitions are recorded side by side in a lengthwise fashion. In perpendicular recording the flux transitions are “stood on end,” as it were. Details of implementation of longitudinal and perpendicular recording are very well known to ordinarily skilled artisans, and so need not be detailed here.
As disk drive data densities have increased, the need to put more flux transitions has become more acute. Perpendicular recording has been known for some time. However, problems associated with performing perpendicular recording have prevented its adoption.
Data recorded on a disk may be retrieved to decode the signals and reproduce the encoded digital data. A read channel reads or receives the encoded data and reproduces the original digital signal. In general, a read channel includes a transducer component that senses the analog signal and digital processing components that detect sequences of changes in the signal that represent encoded digital data. For example, a read channel used in a magnetic storage device includes a transducer head that senses the magnetic flux transitions and produces a continuous analog signal that must then be detected and decoded. In general, the shape of the continuous waveform represents the encoded digital data.
Analog signal processing circuitry, such as amplifiers, filters, and converters, introduces a dc offset that varies as a function of temperature and signal gain resulting in a signal level shift which, if uncorrected can degrade performance of the data recovery system. The dc offset raises or lowers the normal peaks and valleys of the analog signal and the changing levels of the dc offset cause baseline wander that adversely affects the read channel gain, stability and overall quality.
Varying dc offset causes baseline wander, which is low frequency disturbance of a radio frequency signal causing variations in the peak values of a signal. This dc offset can be a problem for both longitudinal and perpendicular recording. In perpendicular recording, the main cause of baseline wander in perpendicular recording is the pre-amplifier and the read channel are ac coupled. The ac coupling acts as a high pass filter. Since the perpendicular recording read back signal contains significant low frequency components, the high pass filter introduces baseline wander.
One known approach to canceling the dc offset is to block dc. Typically, blocking uses ac coupling, wherein a coupling capacitor is placed at the output of the analog circuit element. Blocking can lower dc offset arising on the analog input line. However, it does not remove any dc offset caused by digital signal processing. Thus, blocking is used on the communication line outside the read channel. One disadvantage of dc blocking is that the capacitors necessary for blocking the dc offset occupy considerable chip space, thereby making blocking unsuited for applications when a read channel is implemented on an integrated circuit. Accordingly, blocking is not a very effective technique for handling dc offset in a read channel.
Another approach, shown in FIG. 2, provides a feedback loop to remove as much of the dc noise as possible. In FIG. 2, an analog input signal passes through a filter, such as continuous time filter (CTF) 202, and is subtracted from a dc correction signal to form a corrected analog signal. An analog-to-digital converter (ADC) 204 samples the corrected analog signal to provide a digital signal. This digital signal passes through a finite impulse response (FIR) filter 205 to remove intersymbol interference, and then to a Viterbi algorithm bit detector 207. The bit detector 207 provides a digital estimate of the analog input signal. A summer subtracts the output of the bit detector from the input of the bit detector to form an error signal e0. This error signal is the difference between estimated data and the sampled data.
The error signal enters a loop filter 211, and is biased with a constant loop gain, μ1, and then is summed with the current value of the dc correction signal. The current value of the dc correction signal results from delaying the biased error signal. The dc correction signal is converted to an analog signal with a digital to analog converter (DAC) 228 and then is summed with the filtered input signal.
Copending, commonly assigned application Ser. No. 09/536,120 filed Mar. 27, 2000 (now U.S. Pat. No. 6,856,790), incorporated herein by reference, shows still another approach wherein the dc correction circuitry has a first and a second feedback loop. Referring now to FIG. 3, a summer subtracts the output from the input of the bit detector from the input to form an error signal e0. This error signal is the difference between estimated data and the sampled data. This error signal, e0, provides the input to the first dc feedback loop, including a first loop filter 311. The first loop filter 311 includes a first biasing circuit, which is connected to the input to receive the error signal and to multiply the error signal by a first loop gain constant to produce a first product. The first product is an input to a first summer circuit. The first summer circuit is additionally connected to the output of the first dc feedback loop to receive a current first dc noise cancellation signal. The first summer circuit adds the first product with the current first dc offset cancellation signal to produce a next first dc offset cancellation signal. An accumulator circuit is connected to the first summer circuit to produce the feedback loop output.
A second summer combines the error signal, e0, and the output of the first feedback loop thereby restoring the first error correction signal. The output of that second summer is input to a second dc feedback loop, including a second loop filter 313. In the second loop filter 313, a second biasing circuit combines the restored first error correction signal and a second loop gain constant, μ2, to form a second product that is an input to a third summer circuit. The third summer circuit is additionally connected to the output of the second dc feedback loop to receive a current second dc offset cancellation signal. The third summer circuit adds the second product with the current second dc offset cancellation signal to produce a next second dc offset cancellation signal. A second accumulator is connected to the third summer circuit to produce the second dc offset cancellation signal. The second dc offset cancellation signal then passes to an digital-to-analog (DAC) converter 328 and is then recombined with the input signal.